Binary tree topology generally fails to attract network on chip (NoC) implementations due to its low bisection bandwidth. Fat trees\nare proposed to alleviate this issue by using increasingly thicker links to connect switches towards the root node.This scheme is very\nefficient in interconnected networks such as computer networks,which use generic switches for interconnection. In anNoCcontext,\nespecially for field programmable gate arrays (FPGAs), fat trees requiremore complex switches as we move higher in the hierarchy.\nThis restricts the maximum clock frequency at which the network operates and offsets the higher bandwidth achieved through\nusing fatter links. In this paper, we discuss the implementation of a binary tree-based NoC, which achieves better bandwidth by\nvarying the clock frequency between the switches as we move higher in the hierarchy. This scheme enables using simpler switch\narchitecture, thus supporting higher maximum frequency of operation. The effect on bandwidth and resource requirement of this\narchitecture is compared with other FPGA-based NoCs for different network sizes and traffic patterns.
Loading....